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(where A´ is a material-dependent constant, and
EF is the Fermi energy), as can be seen by a com-
parison with the functional dependence G º
exp[–A(Ncut – N0)
1/2
](where G is the conduct-
ance across the barrier, and A and N0 are dimen-
sionless fitting parameters).We conclude that the
barrier written by the AFM tip acts as a tunnel
junction that interrupts the written nanowires.
SketchFET. The ability to produce ultrathin
potential barriers in nanowires enables the creation
of field-effect devices with strongly nonlinear char-
acteristics. We demonstrate two families of such
devices. Both begin with a “T-junction” of na-
nowire leads written with Vtip =10V(w ~12nm)

(fig. S3A). As constructed, the T-junction be-
haves as a simple resistive network (fig. S3B).
The creation of the first device (Fig. 2A) begins
with erasing the central region (within 1 mmfrom
the center) of a T-junction of source, gate, and drain
electrodes and then reconnecting the channels with
Vtip =3V(w ~ 2 nm), followed by a subtractive
step in which the AFM probe is scanned under
negative bias (Vtip = –3 V), starting from the center
of the junction across the source-drain channel and
moving a gap distance g2 = 50 nm along the di-
rection of the gate electrode. This step also creates
a barrier g1 = 2 nm between source and drain. The
asymmetry in the two gaps (fig. S4A) enables the
gate electrode to modulate the source-drain con-
ductance with minimal gate leakage current. We
refer to this device as a SketchFET (sketch-defined
electronic transport within a complex-oxide het-
erostructure field-effect transistor).
Transport measurements of this SketchFET
are performed by monitoring the drain current ID
as a function of the source and gate voltages (VSD
and VGD, respectively). Both VSD and VGD are
referenced to the drain, which is held at virtual
ground. At zero gate bias, the I-V characteristic
between source and drain is highly nonlinear and
nonconducting at small |VSD| (Fig. 2B). A posi-
tive gate bias VGD > 0 lowers the potential barrier
for electrons in the source and gate leads. With
VGD large enough (≥4 V in this specific device),
the barrier eventually disappears. In this regime,
ohmic behavior between source and drain is
observed. The field effect in this case is non-
hysteretic, in contrast to field effects induced by
the AFM probe (24). At negative gate biases the
nonlinearity is enhanced, and a gate-tunable
negative-differential resistance (NDR) is observed
for VSD > –2.5 V. When a sufficiently large gate
bias is applied, a small gate leakage current IGD
also contributes to the total drain current ID (fig.
S4A). The NDR regime is associated with this
gate leakage current (see below).
By increasing the source-drain gap (g1 =12
nm) of the SketchFET (fig. S5), the source-drain
characteristic becomes more symmetric. This struc-
ture requires a larger positive gate bias to switch
the channel on. Tunneling through such a wide
barrier width is highly unusual, but it is assisted
by the triangular nature of the tunneling barrier
under large applied fields (on the order ofMV/cm),
and the barrier width is renormalized by the large
dielectric constant of SrTiO3 (e ~ 300 at room
temperature).
One of the most important technological ap-
plications of FETs is making logic elements. The
applied values of VSD and VGD can be interpreted
as “on” (>4 V) or “off” (<4 V) input states of a
logic device; the measured values of ID can be